System DMA Block

Overview

The System DMA block is a portion of the Vicky II chip which is responsible for high speed memory transfers to or from system memory. The block supports several types of memory operations:

• Copying a contiguous block of data from one section of memory to another (1D or linear transfers)
• Copying a rectangular subset of a larger image from one section of memory to another (2D or block transfers)
• Filling a contiguous block of addresses in video memory with a single byte (1D fill)
• Filling a rectangular subset of a larger image with a single byte (2D fill)

SDMA can copy data between different locations within system RAM, it can be used in conjunction with the Video DMA Block to transfer data between video RAM and system RAM.

IMPORTANT! SDMA halts the processor while it is in operation. The CPU will be unable to perform any tasks while an SDMA transfer is in operation. This includes handling interrupts of any sort.

Setting up a SDMA

The process of starting a SDMA is as follows:

1. Set the SDMA_CONTROL_REG0 bits to enable the SDMA block, set 1D or 2D operation, set transfer or fill, and indicate if the source or destination is system RAM. If your code will use interrupts, you may enable SDMA interrupts with the SDMA_CTRL0_Int_Enable bit. Do not set SDMA_CTRL0_Start_TRF at this point.
2. If the source of the data is in system RAM, set SDMA_SRC_ADDY.
3. If the destination of the data is in system RAM, set SDMA_DST_ADDY.
4. If the transfer is a 1D operation, set the size (number of bytes) in SDMA_SIZE. If the transfer is a 2D operation, set the width in SDMA_X_SIZE, and the height in SDMA_Y_SIZE.
5. If the transfer is a 2D operation, set the source and destination stride values.
6. Set the SDMA_CTRL0_Start_TRF bit of SDMA_CONTROL_REG0 to begin the actual transfer.

NOTE: If you are transferring data between system RAM and video RAM, you will have to set up both an SDMA and a VDMA operation, which has special considerations. Please see System and Video RAM DMA for details.

System DMA Registers

Start Address	Stop Address	Register Description	Additional Info
$AF:0420	$AF:0420	SDMA_CTRL_REG0	SDMA control register 0 Bit Name Purpose $01 SDMA_CTRL0_Enable Enable the SDMA block $02 SDMA_CTRL0_1D_2D 0 - 1D (Linear) Transfer , 1 - 2D (Block) Transfer $04 SDMA_CTRL0_TRF_Fill Set to 1 to Enable the Generation of Interrupt when the Transfer is over. $08 SDMA_CTRL0_Int_Enable 0 - Transfer Src -> Dst, 1 - Fill Destination with "Byte2Write" $10 SDMA_CTRL0_SysRAM_Src Set to 1 to Indicate that the Source is the System Ram Memory when transferring out of SRAM. $20 SDMA_CTRL0_SysRAM_Dst Set to 1 to Indicate that the Destination is the System Ram Memory when transferring from outside SRAM. $80 SDMA_CTRL0_Start_TRF Set to 1 to start the transfer.
$AF:0421	$AF:0421	SDMA_CTRL_REG1	Reserved for future use
$AF:0422	$AF:0424	SDMA_SRC_ADDY	24-bit address of the source (if system RAM is the source)
$AF:0425	$AF:0427	SDMA_DST_ADDY	24-bit address of the destination (if system RAM is the destination)
$AF:0428	$AF:042A	SDMA_SIZE	If 1D transfer, the size of the transfer in bytes (24-bits).
$AF:0428	$AF:0429	SDMA_X_SIZE	If 2D transfer, the 16-bit width of the block.
$AF:042A	$AF:042B	SDMA_Y_SIZE	If 2D transfer, the 16-bit height of the block.
$AF:042C	$AF:042D	SDMA_SRC_STRIDE	If 2D transfer, the number of bytes per row in the over-all source image (16-bits).
$AF:042E	$AF:042E	SDMA_DST_STRIDE	If 2D transfer, the number of bytes per row in the over-all destination image (16-bits).
$AF:0430	$AF:0430	SDMA_STATUS_REG / SDMA_BYTE_2_WRITE	On write, the byte to write to memory. On read, the status of the SDMA: Bit Name Purpose $01 SDMA_STAT_Size_Err If Set to 1, Overall Size is Invalid $02 SDMA_STAT_Dst_Add_Err If Set to 1, Destination Address Invalid $04 SDMA_STAT_Src_Add_Err If Set to 1, Source Address Invalid $08 SDMA_STAT_TimeOut_Err If Set to 1, a timeout occurred when transferring between data from and to VRAM

SDMA_CTRL_REG0

This register is the main control register for system DMA. The bits are explained in the table above, but the source and destination bits deserve further attention here. The bits should be interpreted as a pair:

SDMA_CTRL0_SysRAM_Src	SDMA_CTRL0_SysRAM_Dst	Tranfer
0	0	SRAM to SRAM
1	0	SRAM to VRAM
0	1	VRAM to SRAM
1	1	Reserved

SDMA_SRC_ADDY

This register is the 3-byte address of the source of the data (if it is in system RAM).

SDMA_DST_ADDY

This register is the 3-byte address of the destination of the data (if it is in system RAM).

SDMA Size

The size of the block to transfer is specified in one of two ways. For a 1-D or linear transfer (bit SDMA_CTRL_1D_2D in the control register is clear), the size is specified as a 24-bit integer using SDMA_SIZE_L, SDMA_SIZE_M, and SDMA_SIZE_H. If the transfer is a 2-D or block transfer (bit SDMA_CTRL_1D_2D in the control register is set), the size is specified as a 16-bit width stored in SDMA_X_SIZE_L and SDMA_X_SIZE_H, and a 16-bit height stored in SDMA_Y_SIZE_L and SDMA_Y_SIZE_L.

Stride

For a 2-D transfer, there is the notion of a "stride," which is the total number of bytes in a row of a source or destination image. The block being transferred may be narrower than the total image. The stride along with the width of the block tells Vicky how many bytes to skip between rows. Source and destination images can have different widths and therefore different strides. The stride of the source is specified by the two-byte register SDMA_SRC_STRIDE, and the stride of the destination by SDMA_DST_STRIDE.

The relationship between stride, width, and height of a block can be seen in the diagram below: