Difference between revisions of "Gadget:Gen-X"
Jump to navigation
Jump to search
| Line 11: | Line 11: | ||
* The Gen-X on the 68k side appears to be an A2560K; preliminary documentation is [https://256-foenix.us-east-1.linodeobjects.com/A2560K_UM_Rev0.0.2.pdf Here]. | * The Gen-X on the 68k side appears to be an A2560K; preliminary documentation is [https://256-foenix.us-east-1.linodeobjects.com/A2560K_UM_Rev0.0.2.pdf Here]. | ||
| + | * The Gen-X on the 68k side appears to be an FMX. | ||
Memory | Memory | ||
| Line 19: | Line 20: | ||
* Stef says to avoid using the DRAM for now. | * Stef says to avoid using the DRAM for now. | ||
| − | I/O | + | I/O (68k) |
* Power and SD Card LED control bits at GAVIN:0000 (feca) don't appear to work. | * Power and SD Card LED control bits at GAVIN:0000 (feca) don't appear to work. | ||
Revision as of 17:28, 27 June 2023
Getting Started
- Both displays show logos, but only display B is responsive.
Startup
- On hard-reset, the FPGA copies the first 64k of flash to $0.
- Post-upload reset leaves that block alone, so you can upload code there.
Documentation
- The Gen-X on the 68k side appears to be an A2560K; preliminary documentation is Here.
- The Gen-X on the 68k side appears to be an FMX.
Memory
- MOVE16 presently only works with the SRAM in the first 4MB.
- This basically means you can't cache anything anywhere else.
- TODO: test burst mode from the flash (ie can cache and/or keep MMU tables here?)
- Stef says to avoid using the DRAM for now.
I/O (68k)
- Power and SD Card LED control bits at GAVIN:0000 (feca) don't appear to work.
- I can't seem to get the LFSR to work.
- The I/O space should be marked as serialized/no-cache (defaults to unserialized -- reads can get ahead of writes).
vasm
- The 68040 MOVEC cache and MMU control registers are there, but typically without the last letter (R for Register).
