Difference between revisions of "Tiles"
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For each successive tileset, add +4 to the address registers. | For each successive tileset, add +4 to the address registers. | ||
| + | |||
| + | The Addresses are specified with the Video RAM offset of $B0:0000 (i.e. substract $B0:0000 from the address when writing the address). | ||
| + | |||
| + | The Tileset Configuration Register is shown below: | ||
| + | {| {{Wikitable}} | ||
| + | !Attribute | ||
| + | !Bit | ||
| + | |- | ||
| + | |TileStride 256|| Bit 3 | ||
| + | |} | ||
| + | |||
| + | Setting the TileStride allows designer to provide tiles as a bitmap sheet 256 pixel wide. | ||
Revision as of 19:46, 27 June 2021
Vicky II support 8 tilesets and 4 tilemaps.
Tiles
Tiles are tiny reusable bitmaps that are 16 pixels wide by 16 pixels high.
Tilesets
Tiles are combined in tilesets. Tilesets usually contain only unique tiles to save memory. Tilesets can contain a maximum of 256 tiles. Each tile has a unique number in the tileset. Tilesets must be stored in video RAM for Vicky II to be able to render them.
Tilemaps
Tilemaps combine tiles from the tilesets to create a world map. Tilemaps can be up to 1024 tiles wide by 1024 tiles high. Tilemaps must be stored in video RAM in order for Vicky II to render them.
Tilemap Registers
Each Tilemap has registers composed of a total of 12 bytes for manipulation, starting at $AF:0200 and spanning through to $AF:022F.
The first set of Tilemap manipulation registers are shown below:
| Attribute | Address |
|---|---|
| TL0_CONTROL_REG | = $AF:0200 |
| TL0_START_ADDY_L | = $AF:0201 |
| TL0_START_ADDY_M | = $AF:0202 |
| TL0_START_ADDY_H | = $AF:0203 |
| TL0_TOTAL_X_SIZE_L | = $AF:0204 |
| TL0_TOTAL_X_SIZE_H | = $AF:0205 |
| TL0_TOTAL_Y_SIZE_L | = $AF:0206 |
| TL0_TOTAL_Y_SIZE_H | = $AF:0207 |
| TL0_WINDOW_X_POS_L | = $AF:0208 |
| TL0_WINDOW_X_POS_H | = $AF:0209 |
| TL0_WINDOW_Y_POS_L | = $AF:020A |
| TL0_WINDOW_Y_POS_H | = $AF:020B |
| TL1_CONTROL_REG | $AF:020C |
| TL2_CONTROL_REG | $AF:0218 |
| TL3_CONTROL_REG | $AF:0224 |
For each successive tilemap, add +12 to the address registers.
The tilemap control register (TLx_CONTROL_REG) is always the first byte of the 12 byte block. The register is configured as follows:
| Attribute | Bit |
|---|---|
| TILE_Enable | = $01 |
| TILE_Collision_On | = $40 |
The Tilemap Total Size X and Y must be less than 1024.
The Tilemap Window Position X and Y are defined as follows:
| Attribute | Bit |
|---|---|
| Direction | Bit 14 ($4000) |
| Scroll | Bits 10-13 ($4xx to $3Cxx) |
| Position | = 0 to $3FF |
NOTE: each tile referenced by the tilemap uses 2 bytes (16 bits). The first byte is the tile number. The second byte is configured as follows:
| Attribute | Bit |
|---|---|
| Tileset | Bit 0-2 (8 possible tileset) |
| LUT | Bits 3-5 (8 possible LUTs) |
Tileset Registers
Each Tileset has registers composed of a total of 4 bytes for manipulation, starting at $AF:0280 and spanning through to $AF:029F.
The first set of Tileset manipulation registers are shown below:
| Attribute | Address |
|---|---|
| TILESET0_ADDY_L | = $AF:0280 |
| TILESET0_ADDY_M | = $AF:0281 |
| TILESET0_ADDY_H | = $AF:0282 |
| TILESET0_ADDY_CFG | = $AF:0283 |
| TILESET1_ADDY_L | = $AF0284 |
| TILESET2_ADDY_L | = $AF0288 |
| TILESET3_ADDY_L | = $AF028C |
| TILESET4_ADDY_L | = $AF0290 |
| TILESET5_ADDY_L | = $AF0294 |
| TILESET6_ADDY_L | = $AF0298 |
| TILESET7_ADDY_L | = $AF029C |
For each successive tileset, add +4 to the address registers.
The Addresses are specified with the Video RAM offset of $B0:0000 (i.e. substract $B0:0000 from the address when writing the address).
The Tileset Configuration Register is shown below:
| Attribute | Bit |
|---|---|
| TileStride 256 | Bit 3 |
Setting the TileStride allows designer to provide tiles as a bitmap sheet 256 pixel wide.
