Difference between revisions of "System DMA Block"

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(Created page with "= Overview = = Setting up a SDMA = = System DMA Registers =")
 
(→‎System DMA Registers)
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= System DMA Registers =
 
= System DMA Registers =
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{| class = "wikitable"
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! Start Address
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! Stop Address
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! Register Description
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! Additional Info
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|-
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| $AF:0420 || $AF:0420 || SDMA_CTRL_REG0|| SDMA control register 0
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{| class = "wikitable"
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! Bit
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! Name
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! Purpose
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|-
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| $01 || SDMA_CTRL0_Enable || Enable the SDMA block
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|-
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| $02 || SDMA_CTRL0_1D_2D || 0 - 1D (Linear) Transfer , 1 - 2D (Block) Transfer
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|-
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| $04 || SDMA_CTRL0_TRF_Fill || Set to 1 to Enable the Generation of Interrupt when the Transfer is over.
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|-
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| $08 || SDMA_CTRL0_Int_Enable || 0 - Transfer Src -> Dst, 1 - Fill Destination with "Byte2Write"
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|-
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| $10 || SDMA_CTRL0_SysRAM_Src || Set to 1 to Indicate that the Source is the System Ram Memory
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|-
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| $20 || SDMA_CTRL0_SysRAM_Dst || Set to 1 to Indicate that the Destination is the System Ram Memory
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|-
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| $80 || SDMA_CTRL0_Start_TRF || Set to 1 to start the transfer.
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|}
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|-
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| $AF:0421 || $AF:0421 || SDMA_CTRL_REG1 || System DMA Control Register 1
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|-
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| $AF:0422 || $AF:0422 || SDMA_SRC_ADDY_L || 24-bit address of the source (if system RAM is the source)
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|-
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| $AF:0423 || $AF:0423 || SDMA_SRC_ADDY_M
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|-
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| $AF:0424 || $AF:0424 || SDMA_SRC_ADDY_H
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|-
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| $AF:0425 || $AF:0425 || SDMA_DST_ADDY_L || 24-bit address of the destination (if system RAM is the destination)
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|-
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| $AF:0426 || $AF:0426 || SDMA_DST_ADDY_M
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|-
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| $AF:0427 || $AF:0427 || SDMA_DST_ADDY_H
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|-
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| $AF:0428 || $AF:0428 || SDMA_SIZE_L / SDMA_X_SIZE_L || If 1D transfer, the size of the transfer in bytes (24-bits). If 2D transfer, the 16-bit width of the block.
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|-
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| $AF:0429 || $AF:0429 || SDMA_SIZE_M / SDMA_X_SIZE_H
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|-
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| $AF:042A || $AF:042A || SDMA_SIZE_H / SDMA_Y_SIZE_L || If 2D transfer, the 16-bit height of the block.
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|-
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| $AF:042B || $AF:042B || Ignored / SDMA_Y_SIZE_H
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|-
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| $AF:042C || $AF:042C || SDMA_SRC_STRIDE_L || If 2D transfer, the number of bytes per row in the over-all source image.
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|-
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| $AF:042D || $AF:042D || SDMA_SRC_STRIDE_H
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|-
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| $AF:042E || $AF:042E || SDMA_DST_STRIDE_L
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|-
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| $AF:042F || $AF:042F || SDMA_DST_STRIDE_H || If 2D transfer, the number of bytes per row in the over-all destination image.
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|-
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| $AF:0430 || $AF:0430 || SDMA_STATUS_REG / SDMA_BYTE_2_WRITE || On write, the byte to write to memory.
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On read, the status of the SDMA:
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{| class = "wikitable"
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! Bit
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! Name
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! Purpose
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|-
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| $01 || SDMA_STAT_Size_Err || If Set to 1, Overall Size is Invalid
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|-
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| $02 || SDMA_STAT_Dst_Add_Err || If Set to 1, Destination Address Invalid
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|-
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| $04 || SDMA_STAT_Src_Add_Err || If Set to 1, Source Address Invalid
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|-
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| $08 || SDMA_STAT_TimeOut_Err || If Set to 1, a timeout occurred when transferring between data from and to VRAM
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|}

Revision as of 12:50, 18 January 2021

Overview

Setting up a SDMA

System DMA Registers

Start Address Stop Address Register Description Additional Info
$AF:0420 $AF:0420 SDMA_CTRL_REG0 SDMA control register 0
Bit Name Purpose
$01 SDMA_CTRL0_Enable Enable the SDMA block
$02 SDMA_CTRL0_1D_2D 0 - 1D (Linear) Transfer , 1 - 2D (Block) Transfer
$04 SDMA_CTRL0_TRF_Fill Set to 1 to Enable the Generation of Interrupt when the Transfer is over.
$08 SDMA_CTRL0_Int_Enable 0 - Transfer Src -> Dst, 1 - Fill Destination with "Byte2Write"
$10 SDMA_CTRL0_SysRAM_Src Set to 1 to Indicate that the Source is the System Ram Memory
$20 SDMA_CTRL0_SysRAM_Dst Set to 1 to Indicate that the Destination is the System Ram Memory
$80 SDMA_CTRL0_Start_TRF Set to 1 to start the transfer.
$AF:0421 $AF:0421 SDMA_CTRL_REG1 System DMA Control Register 1
$AF:0422 $AF:0422 SDMA_SRC_ADDY_L 24-bit address of the source (if system RAM is the source)
$AF:0423 $AF:0423 SDMA_SRC_ADDY_M
$AF:0424 $AF:0424 SDMA_SRC_ADDY_H
$AF:0425 $AF:0425 SDMA_DST_ADDY_L 24-bit address of the destination (if system RAM is the destination)
$AF:0426 $AF:0426 SDMA_DST_ADDY_M
$AF:0427 $AF:0427 SDMA_DST_ADDY_H
$AF:0428 $AF:0428 SDMA_SIZE_L / SDMA_X_SIZE_L If 1D transfer, the size of the transfer in bytes (24-bits). If 2D transfer, the 16-bit width of the block.
$AF:0429 $AF:0429 SDMA_SIZE_M / SDMA_X_SIZE_H
$AF:042A $AF:042A SDMA_SIZE_H / SDMA_Y_SIZE_L If 2D transfer, the 16-bit height of the block.
$AF:042B $AF:042B Ignored / SDMA_Y_SIZE_H
$AF:042C $AF:042C SDMA_SRC_STRIDE_L If 2D transfer, the number of bytes per row in the over-all source image.
$AF:042D $AF:042D SDMA_SRC_STRIDE_H
$AF:042E $AF:042E SDMA_DST_STRIDE_L
$AF:042F $AF:042F SDMA_DST_STRIDE_H If 2D transfer, the number of bytes per row in the over-all destination image.
$AF:0430 $AF:0430 SDMA_STATUS_REG / SDMA_BYTE_2_WRITE On write, the byte to write to memory.

On read, the status of the SDMA:

Bit Name Purpose
$01 SDMA_STAT_Size_Err If Set to 1, Overall Size is Invalid
$02 SDMA_STAT_Dst_Add_Err If Set to 1, Destination Address Invalid
$04 SDMA_STAT_Src_Add_Err If Set to 1, Source Address Invalid
$08 SDMA_STAT_TimeOut_Err If Set to 1, a timeout occurred when transferring between data from and to VRAM
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