Difference between revisions of "Feature Status"
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| || '''[[A2560U]]''' || '''[[FA2560K]]''' || '''[[A2560M]]''' || '''[[A2560M-Pro]]''' || '''[[A2560K]]''' || '''[[A2560X]]''' || '''[[Gen-X]]''' || '''[[Gen-X2]]''' || | | || '''[[A2560U]]''' || '''[[FA2560K]]''' || '''[[A2560M]]''' || '''[[A2560M-Pro]]''' || '''[[A2560K]]''' || '''[[A2560X]]''' || '''[[Gen-X]]''' || '''[[Gen-X2]]''' || | ||
|- | |- | ||
| − | | Load || || | + | | Load || || MemtextAug30th || || || 0000011.00000 || || || || |
|- | |- | ||
| − | | EXT SID || N/A || N/A || N/A || N/A || || || | + | | EXT SID || N/A || N/A || N/A || N/A || || || || || |
|- | |- | ||
| MMU || N/A || N/A || || || || || Working! || || | | MMU || N/A || N/A || || || || || Working! || || | ||
| Line 24: | Line 24: | ||
| PSG || || || Working! || || || || || || | | PSG || || || Working! || || || || || || | ||
|- | |- | ||
| − | | INT SID || || || Working! || || || || | + | | INT SID || || || Working! || || || || || || |
|- | |- | ||
| PS2 || || || Working! || || || || Inconsistent || || | | PS2 || || || Working! || || || || Inconsistent || || | ||
Latest revision as of 17:30, 24 October 2025
| A2560U | FA2560K | A2560M | A2560M-Pro | A2560K | A2560X | Gen-X | Gen-X2 | ||
| Load | MemtextAug30th | 0000011.00000 | |||||||
| EXT SID | N/A | N/A | N/A | N/A | |||||
| MMU | N/A | N/A | Working! | ||||||
| Cache | N/A | N/A | Working! | ||||||
| DRAM | N/A | 32-64 unstable | Unusable | ||||||
| Ethernet | N/A | Working! | Working! | ||||||
| RTC | Working! | Working! | Working! | ||||||
| INT HD | |||||||||
| EXT SDC | Working! | Working! | |||||||
| WM8776 | Working! | ||||||||
| PSG | Working! | ||||||||
| INT SID | Working! | ||||||||
| PS2 | Working! | Inconsistent | |||||||
| MIDI | Working! | ||||||||
| UARTs | Working! | ||||||||
| MATH | Needs love | working* | |||||||
| VICKY | |||||||||
| Text | Working! | both work! | |||||||
| Bitmap | Working! | ||||||||
| Sprites | Not working | ||||||||
| Tiles | Not working |
- GenX MATH: NOPs needed for divide ops. With optimized caching and pipelining, the CPU's instructions are faster, b/c they don't need to schedule the bus.
- FA2560K TEXT: legacy mode works so long as you don't exceed 8k each of text/attributes; new mode not fully tested, but basics are working!
- 68040/68060: Even with caching disabled, you should still configure the I/O address region(s) for "serialized" access. Otherwise, the memory controller might re-order reads and writes on you!
