Difference between revisions of "Feature Status"
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|- | |- | ||
| UARTs || || || || || || || Working! || || | | UARTs || || || || || || || Working! || || | ||
| + | |- | ||
| + | | MATH || Needs love || || || working* || || || || || | ||
|- | |- | ||
| VICKY | | VICKY | ||
| Line 43: | Line 45: | ||
|- | |- | ||
| Tiles || Not working || || || || || || || || | | Tiles || Not working || || || || || || || || | ||
| − | |||
| − | |||
|} | |} | ||
* GenX MATH: NOPs needed for divide ops. With optimized caching and pipelining, the CPU's instructions are faster, b/c they don't need to schedule the bus. | * GenX MATH: NOPs needed for divide ops. With optimized caching and pipelining, the CPU's instructions are faster, b/c they don't need to schedule the bus. | ||
Revision as of 21:53, 23 October 2025
| A2560U | A2560K | A2560X | Gen-X | Gen-X2 | FA2560K | A2560M | A2560M-Pro | ||
| Load | |||||||||
| DRAM | N/A | 32-64 unstable | Unusable | ||||||
| MMU | N/A | Working! | N/A | ||||||
| Cache | N/A | Working! | N/A | ||||||
| RTC | Working! | Working! | |||||||
| Ethernet | N/A | Working! | |||||||
| INT SD | N/A | N/A | N/A | N/A | N/A | ||||
| EXT SD | Working! | ||||||||
| ATA | N/A | N/A | |||||||
| WM8776 | Working! | ||||||||
| PSG | Working! | ||||||||
| INT SID | Working! | Working! | |||||||
| EXT SID | N/A | Inconsistent | N/A | N/A | |||||
| PS2 | Inconsistent | Working! | |||||||
| MIDI | Working! | ||||||||
| UARTs | Working! | ||||||||
| MATH | Needs love | working* | |||||||
| VICKY | |||||||||
| Text | both work! | ||||||||
| Bitmap | Working! | ||||||||
| Sprites | Not working | ||||||||
| Tiles | Not working |
- GenX MATH: NOPs needed for divide ops. With optimized caching and pipelining, the CPU's instructions are faster, b/c they don't need to schedule the bus.
