Difference between revisions of "Gen-X 68040"
Jump to navigation
Jump to search
| Line 1: | Line 1: | ||
| + | At present, the GenX is functionally equivalent to an A2560K without the keyboard. | ||
| + | |||
[https://256-foenix.us-east-1.linodeobjects.com/A2560K_UM_Rev0.0.2.pdf Manual] | [https://256-foenix.us-east-1.linodeobjects.com/A2560K_UM_Rev0.0.2.pdf Manual] | ||
| Line 5: | Line 7: | ||
Notes: | Notes: | ||
| + | * Both displays show logos, but only display B is responsive. | ||
| + | |||
| + | Startup | ||
| + | |||
| + | * On hard-reset, the FPGA copies the first 64k of flash to $0. | ||
| + | * Post-upload reset leaves that block alone, so you can upload code there. | ||
| + | * Remember that the 68040 has THREE stacks: user, supervisor, and interrupt. Reset puts you on the interrupt stack. | ||
| + | |||
| + | Memory | ||
| + | |||
| + | * With the latest pre-release FPGA load, burst access to SRAM and flash works in all modes. This enables use of the MMU and all of the caching modes. | ||
| + | * If you wish to enable the caches, be sure to mark the I/O space as "serialized". This should technically be done even if you aren't using the dcache. | ||
* At present, the DRAM is not stable. | * At present, the DRAM is not stable. | ||
| + | * To test your own OS code, upload it to $0000:0000. | ||
| + | |||
| + | I/O | ||
| + | * Power and SD Card LED control bits at GAVIN:0000 (feca) don't appear to work. | ||
| + | * If you wish to enable the caches, be sure to mark the I/O space as "serialized". This should technically be done even if you aren't using the dcache. | ||
| + | |||
| + | Math Co-Pro | ||
| + | * Unsigned divide seems broken. | ||
| + | * When running out of iCache, you need a NOP between writing the signed divide registers and reading back the result. | ||
| + | |||
| + | vasm | ||
| + | |||
| + | * The 68040 MOVEC cache and MMU control registers are there, but typically without the last letter (R for Register). | ||
| + | * Auto-alignment rules are brain-damaged: the assembler will re-align instructions but not their associated labels, and won't even warn you if constants are mis-aligned. | ||
| + | ** Ha! The -align option forces natural alignment of data. This fixes most of the problems. Just be sure to manually re-align after any byte data. | ||
Revision as of 10:44, 17 March 2024
At present, the GenX is functionally equivalent to an A2560K without the keyboard.
Latest FPGA release:
Notes:
- Both displays show logos, but only display B is responsive.
Startup
- On hard-reset, the FPGA copies the first 64k of flash to $0.
- Post-upload reset leaves that block alone, so you can upload code there.
- Remember that the 68040 has THREE stacks: user, supervisor, and interrupt. Reset puts you on the interrupt stack.
Memory
- With the latest pre-release FPGA load, burst access to SRAM and flash works in all modes. This enables use of the MMU and all of the caching modes.
- If you wish to enable the caches, be sure to mark the I/O space as "serialized". This should technically be done even if you aren't using the dcache.
- At present, the DRAM is not stable.
- To test your own OS code, upload it to $0000:0000.
I/O
- Power and SD Card LED control bits at GAVIN:0000 (feca) don't appear to work.
- If you wish to enable the caches, be sure to mark the I/O space as "serialized". This should technically be done even if you aren't using the dcache.
Math Co-Pro
- Unsigned divide seems broken.
- When running out of iCache, you need a NOP between writing the signed divide registers and reading back the result.
vasm
- The 68040 MOVEC cache and MMU control registers are there, but typically without the last letter (R for Register).
- Auto-alignment rules are brain-damaged: the assembler will re-align instructions but not their associated labels, and won't even warn you if constants are mis-aligned.
- Ha! The -align option forces natural alignment of data. This fixes most of the problems. Just be sure to manually re-align after any byte data.
