Video DMA Block - Revision history

PJW: /* VDMA Size */

2021-01-19T00:36:13Z

‎VDMA Size

2021-01-19T00:35:02Z

‎Setting up a VDMA

2021-01-19T00:33:46Z

‎Video DMA Registers

2021-01-19T00:22:47Z

‎Stride

2021-01-18T21:40:59Z

‎Setting up a VDMA

2021-01-18T21:38:36Z

2021-01-18T20:28:54Z

2021-01-18T20:14:50Z

‎Overview

2021-01-18T20:10:39Z

2021-01-18T20:05:40Z

‎Video DMA Registers

@@ Line 121: / Line 121: @@
 == VDMA Size ==
-The size of the block to transfer is specified in one of two ways. For a 1-D or linear transfer (bit VDMA_CTRL_1D_2D in the control register is clear), the size is specified as a 24-bit integer using VDMA_SIZE_L, VDMA_SIZE_M, and VDMA_SIZE_H.
+The size of the block to transfer is specified in one of two ways. For a 1-D or linear transfer (bit VDMA_CTRL_1D_2D in the control register is clear), the size is specified as a 24-bit integer using VDMA_SIZE.
 If the transfer is a 2-D or block transfer (bit VDMA_CTRL_1D_2D in the control register is set), the size is specified as a 16-bit width stored
-in VDMA_X_SIZE_L and VDMA_X_SIZE_H, and a 16-bit height stored in VDMA_Y_SIZE_L and VDMA_Y_SIZE_L.
+in VDMA_X_SIZE, and a 16-bit height stored in VDMA_Y_SIZE.
 == Stride ==

@@ Line 25: / Line 25: @@
 # If the source of the data is in video RAM, set VDMA_SRC_ADDY. The address stored here is the offset within video RAM (so relative to $B0:0000).
 # If the destination of the data is in video RAM, set VDMA_DST_ADDY. The address stored here is the offset within video RAM (so relative to $B0:0000).
-# If the transfer is a 1D operation, set the size (number of bytes) in VDMA_SIZE_L, VDMA_SIZE_M, and VDMA_SIZE_H. If the transfer is a 2D operation, set the width in VDMA_X_SIZE_L and VDMA_X_SIZE_H, and the height if VDMA_Y_SIZE_L and VDMA_Y_SIZE_H.
+# If the transfer is a 1D operation, set the size (number of bytes) in VDMA_SIZE. If the transfer is a 2D operation, set the width in VDMA_X_SIZE, and the height in VDMA_Y_SIZE.
 # If the transfer is a 2D operation, set the source and destination stride values.
 # Set the VDMA_CTRL_Start_TRF bit of VDMA_CONTROL_REG to begin the actual transfer.

@@ Line 39: / Line 39: @@
 ! Start Address
 ! Stop Address
-! Register Description
+! Register Name
 ! Additional Info
 |-
@@ Line 84: / Line 84: @@
 |-
-| $AF:0402 || $AF:0402 || VDMA_SRC_ADDY_L || 24-bit address of the source block (relative to start of video RAM)
+| $AF:0402 || $AF:0404 || VDMA_SRC_ADDY || 24-bit address of the source block (relative to start of video RAM)
 |-
-| $AF:0403 || $AF:0403 || VDMA_SRC_ADDY_M
+| $AF:0405 || $AF:0407 || VDMA_DST_ADDY|| 24-bit address of the destination block (relative to start of video RAM)
 |-
-| $AF:0404 || $AF:0404 || VDMA_SRC_ADDY_H
+| $AF:0408 || $AF:040A || VDMA_SIZE || For 1-D DMA, 24-bit size of transfer in bytes.
 |-
-| $AF:0405 || $AF:0405 || VDMA_DST_ADDY_L || 24-bit address of the destination block (relative to start of video RAM)
+| $AF:0408 || $AF:0409 || VDMA_X_SIZE || For 2-D, 16-bit width of block
 |-
-| $AF:0406 || $AF:0406 || VDMA_DST_ADDY_M
+| $AF:040A || $AF:040B || VDMA_Y_SIZE || For 2-D transfer, 16-bit height of block
 |-
-| $AF:0407 || $AF:0407 || VDMA_DST_ADDY_H
+| $AF:040C || $AF:040D || VDMA_SRC_STRIDE || Number of bytes per row in a 2-D source block (16-bits)
 |-
-| $AF:0408 || $AF:0408 || VDMA_SIZE_L / VDMA_X_SIZE_L || For 1-D DMA, 24-bit size of transfer in bytes. For 2-D, 16-bit width of block
+| $AF:040E || $AF:040F || VDMA_DST_STRIDE || Number of bytes per row in a 2-D destination block (16-bits)
-|-
 |}

← Older revision		Revision as of 00:22, 19 January 2021
Line 139:		Line 139:
	The block being transferred may be narrower than the total image. The stride along with the width of the block tells Vicky how many bytes to		The block being transferred may be narrower than the total image. The stride along with the width of the block tells Vicky how many bytes to
	skip between rows. Source and destination images can have different widths and therefore different strides. The stride of the source is specified by the two-byte register VDMA_SRC_STRIDE, and the stride of the destination by VDMA_DST_STRIDE.		skip between rows. Source and destination images can have different widths and therefore different strides. The stride of the source is specified by the two-byte register VDMA_SRC_STRIDE, and the stride of the destination by VDMA_DST_STRIDE.
		+
		+	The relationship between stride, width, and height of a block can be seen in the diagram below:
		+
		+	[[File:Vicky_Stride.png]]

@@ Line 32: / Line 32: @@
 NOTE: If you are transferring data between system RAM and video RAM, you will have to set up both an SDMA and a VDMA operation, which has special considerations.
-Please see [[System_and_Video_RAM_DMA]] for details.
+Please see [[System and Video RAM DMA]] for details.
 = Video DMA Registers =

@@ Line 1: / Line 1: @@
-== Overview ==
+= Overview =
 The Video DMA block is a portion of the Vicky II chip which is responsible for high speed memory transfers to or from video memory.
@@ Line 15: / Line 15: @@
 try to access video RAM while there is a VDMA in operation.
-== Setting up a VDMA ==
+= Setting up a VDMA =
 The process of starting a VDMA is as follows:
@@ Line 21: / Line 21: @@
 clear. This is somewhat optional. If you are certain no VDMA is in flight, you can skip this step.
 # Set the VDMA_CONTROL_REG bits to enable the VDMA block, set 1D or 2D operation, set transfer or fill, and indicate if the source or
-destination is system RAM (see [[System and Video RAM DMA]] for special notes in that case). If your code will use interrupts, you may enable
+destination is system RAM. If your code will use interrupts, you may enable
 VDMA interrupts with the VDMA_CTRL_Int_Enable bit. Do not set VDMA_CTRL_Start_TRF at this point.
 # If the source of the data is in video RAM, set VDMA_SRC_ADDY. The address stored here is the offset within video RAM (so relative to $B0:0000).
@@ Line 31: / Line 31: @@
 # Clear the VDMA_CTRL_Start_TRF bit of VDMA_CONTROL_REG.
-== Video DMA Registers ==
+NOTE: If you are transferring data between system RAM and video RAM, you will have to set up both an SDMA and a VDMA operation, which has special considerations.
 {| class = "wikitable"

@@ Line 7: / Line 7: @@
 * Filling a contiguous block of addresses in video memory with a single byte (1D fill)
 * Filling a rectangular subset of a larger image with a single byte (2D fill)
 == Video DMA Registers ==

← Older revision		Revision as of 20:10, 18 January 2021
Line 1:		Line 1:
		+	== Overview ==
		+
		+	The Video DMA block is a portion of the Vicky II chip which is responsible for high speed memory transfers to or from video memory.
		+	The block supports several types of memory operations:
		+	* Copying a contiguous block of data from one section of memory to another (1D or linear transfers)
		+	* Copying a rectangular subset of a larger image from one section of memory to another (2D or block transfers)
		+	* Filling a contiguous block of addresses in video memory with a single byte (1D fill)
		+	* Filling a rectangular subset of a larger image with a single byte (2D fill)
		+
	== Video DMA Registers ==		== Video DMA Registers ==