System DMA Block - Revision history

PJW: /* System DMA Registers */

2021-01-19T00:59:24Z

‎System DMA Registers

PJW: /* SDMA Size */

2021-01-19T00:56:55Z

‎SDMA Size

PJW: /* SDMA Size */

2021-01-19T00:54:05Z

‎SDMA Size

PJW: /* System DMA Registers */

2021-01-19T00:50:02Z

‎System DMA Registers

PJW at 00:49, 19 January 2021

2021-01-19T00:49:01Z

PJW: /* Stride */

2021-01-19T00:22:07Z

‎Stride

PJW: /* SDMA_DST_ADDY */

2021-01-19T00:10:38Z

‎SDMA_DST_ADDY

PJW: /* SDMA_SRC_ADDY */

2021-01-19T00:10:29Z

‎SDMA_SRC_ADDY

PJW: /* SDMA_CTRL_REG0 */

2021-01-19T00:07:34Z

‎SDMA_CTRL_REG0

PJW: /* System DMA Registers */

2021-01-19T00:05:29Z

‎System DMA Registers

@@ Line 30: / Line 30: @@
 ! Start Address
 ! Stop Address
-! Register Description
+! Register Name
 ! Additional Info
 |-

@@ Line 124: / Line 124: @@
 == SDMA Size ==
-The size of the block to transfer is specified in one of two ways. For a 1-D or linear transfer (bit SDMA_CTRL_1D_2D in the control register is clear), the size is specified as a 24-bit integer using SDMA_SIZE. If the transfer is a 2-D or block transfer (bit SDMA_CTRL_1D_2D in the control register is set), the size is specified as a 16-bit width stored in SDMA_X_SIZE_L and SDMA_X_SIZE_H, and a 16-bit height stored in SDMA_Y_SIZE.
+The size of the block to transfer is specified in one of two ways. For a 1-D or linear transfer (bit SDMA_CTRL_1D_2D in the control register is clear), the size is specified as a 24-bit integer using SDMA_SIZE. If the transfer is a 2-D or block transfer (bit SDMA_CTRL_1D_2D in the control register is set), the size is specified as a 16-bit width stored in SDMA_X_SIZE, and a 16-bit height stored in SDMA_Y_SIZE.
 == Stride ==

@@ Line 124: / Line 124: @@
 == SDMA Size ==
-The size of the block to transfer is specified in one of two ways. For a 1-D or linear transfer (bit SDMA_CTRL_1D_2D in the control register is clear), the size is specified as a 24-bit integer using SDMA_SIZE_L, SDMA_SIZE_M, and SDMA_SIZE_H. If the transfer is a 2-D or block transfer (bit SDMA_CTRL_1D_2D in the control register is set), the size is specified as a 16-bit width stored in SDMA_X_SIZE_L and SDMA_X_SIZE_H, and a 16-bit height stored in SDMA_Y_SIZE_L and SDMA_Y_SIZE_L.
+The size of the block to transfer is specified in one of two ways. For a 1-D or linear transfer (bit SDMA_CTRL_1D_2D in the control register is clear), the size is specified as a 24-bit integer using SDMA_SIZE. If the transfer is a 2-D or block transfer (bit SDMA_CTRL_1D_2D in the control register is set), the size is specified as a 16-bit width stored in SDMA_X_SIZE_L and SDMA_X_SIZE_H, and a 16-bit height stored in SDMA_Y_SIZE.
 == Stride ==

@@ Line 73: / Line 73: @@
 | $AF:042C || $AF:042D || SDMA_SRC_STRIDE || If 2D transfer, the number of bytes per row in the over-all source image (16-bits).
 |-
-| $AF:042E || $AF:042E || SDMA_DST_STRIDE || If 2D transfer, the number of bytes per row in the over-all destination image (16-bits).
+| $AF:042E || $AF:042F || SDMA_DST_STRIDE || If 2D transfer, the number of bytes per row in the over-all destination image (16-bits).
 |-

@@ Line 17: / Line 17: @@
 # If the source of the data is in system RAM, set SDMA_SRC_ADDY.
 # If the destination of the data is in system RAM, set SDMA_DST_ADDY.
-# If the transfer is a 1D operation, set the size (number of bytes) in SDMA_SIZE_L, SDMA_SIZE_M, and SDMA_SIZE_H. If the transfer is a 2D operation, set the width in SDMA_X_SIZE_L and SDMA_X_SIZE_H, and the height if SDMA_Y_SIZE_L and SDMA_Y_SIZE_H.
+# If the transfer is a 1D operation, set the size (number of bytes) in SDMA_SIZE. If the transfer is a 2D operation, set the width in SDMA_X_SIZE, and the height in SDMA_Y_SIZE.
 # If the transfer is a 2D operation, set the source and destination stride values.
 # Set the SDMA_CTRL0_Start_TRF bit of SDMA_CONTROL_REG0 to begin the actual transfer.
@@ Line 57: / Line 57: @@
 | $AF:0421 || $AF:0421 || SDMA_CTRL_REG1 || Reserved for future use
 |-
-| $AF:0422 || $AF:0422 || SDMA_SRC_ADDY_L || 24-bit address of the source (if system RAM is the source)
+| $AF:0422 || $AF:0424 || SDMA_SRC_ADDY || 24-bit address of the source (if system RAM is the source)
 |-
-| $AF:0423 || $AF:0423 || SDMA_SRC_ADDY_M
+| $AF:0425 || $AF:0427 || SDMA_DST_ADDY || 24-bit address of the destination (if system RAM is the destination)
 |-
-| $AF:0424 || $AF:0424 || SDMA_SRC_ADDY_H
+| $AF:0428 || $AF:042A || SDMA_SIZE || If 1D transfer, the size of the transfer in bytes (24-bits).
 |-
-| $AF:0425 || $AF:0425 || SDMA_DST_ADDY_L || 24-bit address of the destination (if system RAM is the destination)
+| $AF:0428 || $AF:0429 || SDMA_X_SIZE || If 2D transfer, the 16-bit width of the block.
 |-
-| $AF:0426 || $AF:0426 || SDMA_DST_ADDY_M
+| $AF:042A || $AF:042B || SDMA_Y_SIZE || If 2D transfer, the 16-bit height of the block.
 |-
-| $AF:0427 || $AF:0427 || SDMA_DST_ADDY_H
+| $AF:042C || $AF:042D || SDMA_SRC_STRIDE || If 2D transfer, the number of bytes per row in the over-all source image (16-bits).
 |-
-| $AF:0428 || $AF:0428 || SDMA_SIZE_L / SDMA_X_SIZE_L || If 1D transfer, the size of the transfer in bytes (24-bits). If 2D transfer, the 16-bit width of the block.
+| $AF:042E || $AF:042E || SDMA_DST_STRIDE || If 2D transfer, the number of bytes per row in the over-all destination image (16-bits).
-|-
 |-
 | $AF:0430 || $AF:0430 || SDMA_STATUS_REG / SDMA_BYTE_2_WRITE || On write, the byte to write to memory.

← Older revision		Revision as of 00:22, 19 January 2021
Line 138:		Line 138:

	For a 2-D transfer, there is the notion of a "stride," which is the total number of bytes in a row of a source or destination image. The block being transferred may be narrower than the total image. The stride along with the width of the block tells Vicky how many bytes to skip between rows. Source and destination images can have different widths and therefore different strides. The stride of the source is specified by the two-byte register SDMA_SRC_STRIDE, and the stride of the destination by SDMA_DST_STRIDE.		For a 2-D transfer, there is the notion of a "stride," which is the total number of bytes in a row of a source or destination image. The block being transferred may be narrower than the total image. The stride along with the width of the block tells Vicky how many bytes to skip between rows. Source and destination images can have different widths and therefore different strides. The stride of the source is specified by the two-byte register SDMA_SRC_STRIDE, and the stride of the destination by SDMA_DST_STRIDE.
		+
		+	The relationship between stride, width, and height of a block can be seen in the diagram below:
		+
		+	[[File:Vicky_Stride.png]]

@@ Line 129: / Line 129: @@
 == SDMA_DST_ADDY ==
-This register is the 3-byte address of the destination of the data (if it is in system RAM or I/O).
+This register is the 3-byte address of the destination of the data (if it is in system RAM).
 == SDMA Size ==

@@ Line 125: / Line 125: @@
 == SDMA_SRC_ADDY ==
-This register is the 3-byte address of the source of the data (if it is in system RAM or I/O).
+This register is the 3-byte address of the source of the data (if it is in system RAM).
 == SDMA_DST_ADDY ==

@@ Line 120: / Line 120: @@
 | 0 || 1 || VRAM to SRAM
 |-
-| 1 || 1 || Transfer to or from I/O (consult SDMA_CTRL_REG1)
+| 1 || 1 || Reserved
 |}

@@ Line 81: / Line 81: @@
 | $AF:042D || $AF:042D || SDMA_SRC_STRIDE_H
 |-
-| $AF:042E || $AF:042E || SDMA_DST_STRIDE_L
+| $AF:042E || $AF:042E || SDMA_DST_STRIDE_L || If 2D transfer, the number of bytes per row in the over-all destination image.
 |-
-| $AF:042F || $AF:042F || SDMA_DST_STRIDE_H || If 2D transfer, the number of bytes per row in the over-all destination image.
+| $AF:042F || $AF:042F || SDMA_DST_STRIDE_H
 |-
 | $AF:0430 || $AF:0430 || SDMA_STATUS_REG / SDMA_BYTE_2_WRITE || On write, the byte to write to memory.