Gen-X 68040 - Revision history

Gadget at 02:44, 6 January 2025

2025-01-06T02:44:48Z

2024-06-26T07:44:13Z

2024-05-17T18:17:30Z

2024-03-17T19:04:41Z

2024-03-17T19:01:55Z

2024-03-17T18:51:58Z

2024-03-17T18:50:49Z

2024-03-17T18:44:21Z

2024-03-15T21:14:37Z

2024-03-15T21:00:53Z

Created page with "[https://256-foenix.us-east-1.linodeobjects.com/A2560K_UM_Rev0.0.2.pdf Manual]"

New page

[https://256-foenix.us-east-1.linodeobjects.com/A2560K_UM_Rev0.0.2.pdf Manual]

@@ Line 33: / Line 33: @@
 LEDs
-* Attempting to disable the motherboard heartbeat LEDs (GAVIN+0) FUBARs the machine.
+* Heartbeat LEDs are controlled by the SuperIO (attempting to disable the motherboard heartbeat LEDs via GAVIN+0 FUBARs the machine!).
 vasm

← Older revision		Revision as of 07:44, 26 June 2024
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	* Invert the polarity of the signal (GAVIN's polarity control doesn't appear to do anything). The lan manual says that this setting is ignored in push/pull mode, but this is apparently not the case...		* Invert the polarity of the signal (GAVIN's polarity control doesn't appear to do anything). The lan manual says that this setting is ignored in push/pull mode, but this is apparently not the case...
	* Clear the condition in the lan before resetting the lan's IRQ. In my case, this means draining the rx queue. This is ... awkward, and could lead to race conditions, but we'll see. Weirdly, clearing it before appears to change the chip's internal report, but not its external report...		* Clear the condition in the lan before resetting the lan's IRQ. In my case, this means draining the rx queue. This is ... awkward, and could lead to race conditions, but we'll see. Weirdly, clearing it before appears to change the chip's internal report, but not its external report...
		+	* Update: On the 816 side, I was able to get a more normal order of operations by disabling the relevant IRQ, clearing it, doing the work, and then re-enabling it.

@@ Line 31: / Line 31: @@
 * Unsigned divide seems broken; might have heard it's using the same inputs as the signed divide.
 * When running out of iCache, you need a NOP between writing the signed divide registers and reading back the result.
 vasm

← Older revision		Revision as of 19:04, 17 March 2024
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	* Auto-alignment rules are brain-damaged: the assembler will re-align instructions but not their associated labels, and won't even warn you if constants are mis-aligned.		* Auto-alignment rules are brain-damaged: the assembler will re-align instructions but not their associated labels, and won't even warn you if constants are mis-aligned.
	** Ha! The -align option forces natural alignment of data. This fixes most of the problems. Just be sure to manually re-align after any byte data.		** Ha! The -align option forces natural alignment of data. This fixes most of the problems. Just be sure to manually re-align after any byte data.
		+
		+	Ethernet
		+
		+	Whoa!!! Finally managed to make lan interrupts work!!! You need to do three things:
		+	* Enable push/pull drive (apparently, there's no pull-up).
		+	* Invert the polarity of the signal (GAVIN's polarity control doesn't appear to do anything). The lan manual says that this setting is ignored in push/pull mode, but this is apparently not the case...
		+	* Clear the condition in the lan before resetting the lan's IRQ. In my case, this means draining the rx queue. This is ... awkward, and could lead to race conditions, but we'll see. Weirdly, clearing it before appears to change the chip's internal report, but not its external report...

@@ Line 29: / Line 29: @@
 Math Co-Pro
-* Unsigned divide seems broken.
+* Unsigned divide seems broken; might have heard it's using the same inputs as the signed divide.
 * When running out of iCache, you need a NOP between writing the signed divide registers and reading back the result.

@@ Line 23: / Line 23: @@
 I/O
-* Power and SD Card LED control bits at GAVIN:0000 (feca) don't appear to work.
+* The SD Card detect bit doesn't appear to work (always thinks a card is present).
 * If you wish to enable the caches, be sure to mark the I/O space as "serialized".  This should technically be done even if you aren't using the dcache.
 * Text display memory is byte-access only.

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 [https://256-foenix.us-east-1.linodeobjects.com/A2560K_UM_Rev0.0.2.pdf Manual]
@@ Line 5: / Line 7: @@
 Notes:
 * At present, the DRAM is not stable.

← Older revision		Revision as of 21:14, 15 March 2024
Line 1:		Line 1:
	[https://256-foenix.us-east-1.linodeobjects.com/A2560K_UM_Rev0.0.2.pdf Manual]		[https://256-foenix.us-east-1.linodeobjects.com/A2560K_UM_Rev0.0.2.pdf Manual]
		+
		+	Latest FPGA release:
		+
		+	Notes:
		+
		+	* At present, the DRAM is not stable.