Gadget:Gen-X - Revision history

Gadget at 06:53, 4 July 2023

2023-07-04T06:53:26Z

2023-06-30T10:09:17Z

2023-06-30T10:07:31Z

2023-06-30T10:05:00Z

2023-06-28T22:35:01Z

2023-06-28T22:32:33Z

2023-06-28T22:26:45Z

2023-06-28T21:38:19Z

2023-06-28T21:37:50Z

2023-06-28T21:37:18Z

@@ Line 20: / Line 20: @@
 ** This basically means you can't cache anything anywhere else.
 ** Ugh.  Burst writes don't seem to be reliable (they appear to be getting out of sync); burst reads appear to be working.
 * Stef says to avoid using the DRAM for now.
 * Because the MMU makes all of its fetches using burst mode, for now, its tables must be in SRAM.

@@ Line 7: / Line 7: @@
 * On hard-reset, the FPGA copies the first 64k of flash to $0.
 * Post-upload reset leaves that block alone, so you can upload code there.
 Documentation

← Older revision		Revision as of 10:07, 30 June 2023
Line 33:		Line 33:

	* The 68040 MOVEC cache and MMU control registers are there, but typically without the last letter (R for Register).		* The 68040 MOVEC cache and MMU control registers are there, but typically without the last letter (R for Register).
−	* Auto-alignment rules are brain-damaged: the assembler will re-align instructions but not their associated labels, and won't even warn you if constants are mis-aligned. ~~Thus,~~ be sure to re-align after any ~~inlined~~ byte ~~tables~~.	+	* Auto-alignment rules are brain-damaged: the assembler will re-align instructions but not their associated labels, and won't even warn you if constants are mis-aligned.
		+	** Ha! The -align option forces natural alignment of data. This fixes most of the problems. Just be sure to manually re-align after any byte data.

@@ Line 18: / Line 18: @@
 ** Confirmed ... can't burst from flash either.
 ** This basically means you can't cache anything anywhere else.
 * Stef says to avoid using the DRAM for now.
 * Because the MMU makes all of its fetches using burst mode, for now, its tables must be in SRAM.

@@ Line 21: / Line 21: @@
 * Because the MMU makes all of its fetches using burst mode, for now, its tables must be in SRAM.
 * The MMU will not dcache table entries, but it can lock up if tables none-the-less end up there.  Motorola recommends avoiding this scenario by disabling caching on MMU table memory.  If this is not possible (as presently on the Foenix), they recommend disabling either the MMU or the dcache during table updates.
 I/O (68k)

@@ Line 16: / Line 16: @@
 * MOVE16 presently only works with the SRAM in the first 4MB.
 ** This basically means you can't cache anything anywhere else.
 * Stef says to avoid using the DRAM for now.
 I/O (68k)
@@ Line 29: / Line 31: @@
 * The 68040 MOVEC cache and MMU control registers are there, but typically without the last letter (R for Register).