GABE - Revision history

PJW: /* GABE Random Number Generator Status and Control ($AF:E886) */

2021-08-02T15:16:51Z

‎GABE Random Number Generator Status and Control ($AF:E886)

PJW: /* GABE Control Registers ($AF:E880 – $AF:E887) */

2021-08-02T15:12:51Z

‎GABE Control Registers ($AF:E880 – $AF:E887)

Bzuidgeest: /* GABE Timer Registers ($00:0160 – $00:016F) */

2020-06-09T19:52:31Z

‎GABE Timer Registers ($00:0160 – $00:016F)

Bzuidgeest: /* GABE Timer Registers ($00:0160 – $00:016F) */

2020-06-09T19:44:14Z

‎GABE Timer Registers ($00:0160 – $00:016F)

Gadget: /* GABE IDE Registers ($AF:E830 – $AF:E839) */

2020-04-13T19:46:36Z

‎GABE IDE Registers ($AF:E830 – $AF:E839)

PJW: /* GABE SDC Interface ($AF:EA00) */

2020-03-14T16:02:00Z

‎GABE SDC Interface ($AF:EA00)

PJW: /* GABE SDC Interface ($AF:EA00) */

2020-03-14T16:00:45Z

‎GABE SDC Interface ($AF:EA00)

PJW at 15:21, 14 March 2020

2020-03-14T15:21:20Z

Gadget: /* GABE Trinity Joystick/Gamepad and DIP Switch Registers ($AF:E800 – $AF:E80E) */

2020-02-20T23:48:38Z

‎GABE Trinity Joystick/Gamepad and DIP Switch Registers ($AF:E800 – $AF:E80E)

Stef: /* GABE Trinity Joystick/Gamepad and DIP Switch Registers ($AF:E800 – $AF:E80E) */

2020-02-16T22:42:23Z

‎GABE Trinity Joystick/Gamepad and DIP Switch Registers ($AF:E800 – $AF:E80E)

← Older revision		Revision as of 15:16, 2 August 2021
Line 781:		Line 781:
	==== GABE Random Number Generator Status and Control ($AF:E886) ====		==== GABE Random Number Generator Status and Control ($AF:E886) ====

		+	{\| class="wikitable"
		+	\|-
		+	! R/W !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
		+	\|-
		+	\| R \|\| GABE_RNG_LFSR_DONE \|\| \|\| \|\| \|\| \|\| \|\| \|\|
		+	\|-
		+	\| W \|\| \|\| \|\| \|\| \|\| \|\| \|\| GABE_RNG_CTRL_DV \|\| GABE_RNG_CTRL_EN
		+	\|}

		+	; GABE_RNG_LFSR_DONE
		+	: Indicates that output = seed database.
		+
		+	; GABE_RNG_CTRL_DV
		+	: After setting the seed value, toggle this bit for the seed be registered.
		+
		+	; GABE_RNG_CTRL_EN
		+	: Enable the LFSR block.

	==== GABE System Status Register ($AF:E887) ====		==== GABE System Status Register ($AF:E887) ====

@@ Line 778: / Line 778: @@
 ; GABE_CTRL_WRM_RST
 : Triggers a warm reset of the board (GABE_RST_AUTH0 must be set to $AD and GABE_RST_AUTH1 to $DE in order to trigger the reset).
 ==== GABE System Status Register ($AF:E887) ====

@@ Line 242: / Line 242: @@
 |}
-=== GABE Timer Registers ($00:0160 – $00:016F) ===
+=== GABE Timer Registers ($00:0160 – $00:017F) ===
 * Timer0 and Timer1 count system clock transitions (14318180Hz)
@@ Line 254: / Line 254: @@
 !Register Name
 !Additional Info
 |-
 | $00:0160 || || TIMER0_CTRL_REG || Timer 0 control register
@@ Line 270: / Line 272: @@
 |-
 | $00:0167 || || TIMER0_CMP_H || Timer 0 compare register high byte, loaded when counting up
 |-
 | $00:0168 || || TIMER1_CTRL_REG || Timer 1 control register
@@ Line 286: / Line 290: @@
 |-
 | $00:016F || || TIMER1_CMP_H || Timer 1 compare register high byte, loaded when counting up
 |-
 |}

@@ Line 243: / Line 243: @@
 === GABE Timer Registers ($00:0160 – $00:016F) ===
 * Timer0 and Timer1 count system clock transitions (14318180Hz)
-* Timer2 is clocked from VICKY's Start-of-Frame output.
+* Timer2 is clocked from VICKY's Start-of-Frame output (50hz).
 === GABE Interrupt Control Registers ($00:0140 &ndash; $00:014B) ===

@@ Line 562: / Line 562: @@
 | $AF:E834 || W || IDE_CLDR_LO || C7 || C6 || C5 || C4 || C3 || C2 || C1 || C0 || Cylinder Number (low)
 |-
-| $AF:E834 || W || IDE_CLDR_HI || C15 || C14 || C13 || C12 || C11 || C10 || C9 || C8 || Cylinder Number (high)
+| $AF:E835 || W || IDE_CLDR_HI || C15 || C14 || C13 || C12 || C11 || C10 || C9 || C8 || Cylinder Number (high)
 |-
-| $AF:E835 || W || IDE_HEAD || 1 || 0 || 1 || M/S || H3 || H2 || H1 || H0 || Head number and Master (0) / Slave(1) device
+| $AF:E836 || W || IDE_HEAD || 1 || 0 || 1 || M/S || H3 || H2 || H1 || H0 || Head number and Master (0) / Slave(1) device
 |-
-| $AF:E836 || W || IDE_CMD_STAT || CMD7 || CMD6 || CMD5 || CMD4 || CMD3 || CMD2 || CMD1 || CMD0 || Send a command to the drive
+| $AF:E837 || W || IDE_CMD_STAT || CMD7 || CMD6 || CMD5 || CMD4 || CMD3 || CMD2 || CMD1 || CMD0 || Send a command to the drive
 |-
-| $AF:E836 || R || IDE_CMD_STAT || BSY || DRDY || DF || DSC || DRQ || CORR || IDX || ERR || Get the status of device. Reading this will clear the Interrupt Registers
+| $AF:E837 || R || IDE_CMD_STAT || BSY || DRDY || DF || DSC || DRQ || CORR || IDX || ERR || Get the status of device. Reading this will clear the Interrupt Registers
 |-
-| $AF:E837 || X || IDE_DATA_LO || D7 || D6 || D5 || D4 || D3 || D2 || D1 || D0 || 16-bit data transfer registers (low byte)
+| $AF:E838 || X || IDE_DATA_LO || D7 || D6 || D5 || D4 || D3 || D2 || D1 || D0 || 16-bit data transfer registers (low byte)
 |-
-| $AF:E838 || X || IDE_DATA_HI || D15 || D14 || D13 || D12 || D11 || D10 || D9 || D8 || 16-bit data transfer registers (high byte)
+| $AF:E839 || X || IDE_DATA_HI || D15 || D14 || D13 || D12 || D11 || D10 || D9 || D8 || 16-bit data transfer registers (high byte)
 |}

@@ Line 710: / Line 710: @@
 ! Address !! R/W !! Name !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0 !! Description
 |-
-| $AF:AE00 || R || SDC_VERSION_REG || colspan="8"|version || Should read 12
+| $AF:EA00 || R || SDC_VERSION_REG || colspan="8"|version || Should read 12
 |-
-| $AF:AE01 || W || SDC_CONTROL_REG || x || x || x || x || x || x || x || RESET || Control register: RESET = 1 resets the core logic. Self clearing.
+| $AF:EA01 || W || SDC_CONTROL_REG || x || x || x || x || x || x || x || RESET || Control register: RESET = 1 resets the core logic. Self clearing.
 |-
-| $AF:AE02 || W || SDC_TRANS_TYPE_REG ||x || x || x || x || x || x || colspan="2"|TRANS || Sets the type of transaction: 0 = Direct, 1 = INIT SD, 2 = Read Block, 3 = Write block
+| $AF:EA02 || W || SDC_TRANS_TYPE_REG ||x || x || x || x || x || x || colspan="2"|TRANS || Sets the type of transaction: 0 = Direct, 1 = INIT SD, 2 = Read Block, 3 = Write block
 |-
-| $AF:AE03 || W || SDC_TRANS_CONTROL_REG || x || x || x || x || x || x || x || START || Start transaction bit.
+| $AF:EA03 || W || SDC_TRANS_CONTROL_REG || x || x || x || x || x || x || x || START || Start transaction bit.
 |-
-| $AF:AE04 || R || SDC_TRANS_STATUS_REG || x || x || x || x || x || x || x || BUSY || Status of the transaction. BUSY = 1 indicates a transaction is in progress.
+| $AF:EA04 || R || SDC_TRANS_STATUS_REG || x || x || x || x || x || x || x || BUSY || Status of the transaction. BUSY = 1 indicates a transaction is in progress.
 |-
-| $AF:AE05 || R || SDC_TRANS_ERROR_REG || x || x || colspan="2"|WR_ERR || colspan="2"|RD_ERR || colspan="2"|TRANS_ERR || Error conditions for read, write, and transaction.
+| $AF:EA05 || R || SDC_TRANS_ERROR_REG || x || x || colspan="2"|WR_ERR || colspan="2"|RD_ERR || colspan="2"|TRANS_ERR || Error conditions for read, write, and transaction.
 |-
-| $AF:AE06 || RW || SDC_DIRECT_ACCESS_REG || colspan="8"|data || SPI Direct Read and Write - Set DATA before initiating direct Access Transaction
+| $AF:EA06 || RW || SDC_DIRECT_ACCESS_REG || colspan="8"|data || SPI Direct Read and Write - Set DATA before initiating direct Access Transaction
 |-
-| $AF:AE07 || W || SDC_SD_ADDR_7_0_REG || A7 || A6 || A5 || A4 || A3 || A2 || A1 || A0 || Set the ADDR before a block read or block write.
+| $AF:EA07 || W || SDC_SD_ADDR_7_0_REG || A7 || A6 || A5 || A4 || A3 || A2 || A1 || A0 || Set the ADDR before a block read or block write.
 |-
-| $AF:AE08 || W || SDC_SD_ADDR_15_8_REG || A15 || A14 || A13 || A12 || A11 || A10 || A9 || A8 || ADDR[8:0] always should be 0, since each block is 512 bytes
+| $AF:EA08 || W || SDC_SD_ADDR_15_8_REG || A15 || A14 || A13 || A12 || A11 || A10 || A9 || A8 || ADDR[8:0] always should be 0, since each block is 512 bytes
 |-
-| $AF:AE09 || W || SDC_SD_ADDR_23_16_REG || A23 || A22 || A21 || A20 || A19 || A18 || A7 || A6
+| $AF:EA09 || W || SDC_SD_ADDR_23_16_REG || A23 || A22 || A21 || A20 || A19 || A18 || A7 || A6
 |-
-| $AF:AE0A || W || SDC_SD_ADDR_31_24_REG || A32 || A31 || A30 || A29 || A28 || A26 || A25 || A24
+| $AF:EA0A || W || SDC_SD_ADDR_31_24_REG || A32 || A31 || A30 || A29 || A28 || A26 || A25 || A24
 |-
-| $AF:AE0B || W || SDC_SPI_CLK_DEL_REG || colspan="8"|clock delay
+| $AF:EA0B || W || SDC_SPI_CLK_DEL_REG || colspan="8"|clock delay
 |-
-| $AF:AE10 || R || SDC_RX_FIFO_DATA_REG || colspan="8"|data || Data from block read
+| $AF:EA10 || R || SDC_RX_FIFO_DATA_REG || colspan="8"|data || Data from block read
 |-
-| $AF:AE12 || R || SDC_RX_FIFO_DATA_CNT_HI || CNT15 || CNT14 || CNT13 || CNT12 || CNT11 || CNT10 || CNT9 || CNT8 || How many bytes in the read FIFO (HI)
+| $AF:EA12 || R || SDC_RX_FIFO_DATA_CNT_HI || CNT15 || CNT14 || CNT13 || CNT12 || CNT11 || CNT10 || CNT9 || CNT8 || How many bytes in the read FIFO (HI)
 |-
-| $AF:AE13 || R || SDC_RX_FIFO_DATA_CNT_LO || CNT7 || CNT6 || CNT5 || CNT4 || CNT3 || CNT2 || CNT1 || CNT0 || How many bytes in the read FIFO (LOW)
+| $AF:EA13 || R || SDC_RX_FIFO_DATA_CNT_LO || CNT7 || CNT6 || CNT5 || CNT4 || CNT3 || CNT2 || CNT1 || CNT0 || How many bytes in the read FIFO (LOW)
 |-
-| $AF:AE14 || W || SDC_RX_FIFO_CTRL_REG || x || x || x || x || x || x || x || CLEAR || CLEAR = 1, clear the read FIFO. Bit is self-clearing.
+| $AF:EA14 || W || SDC_RX_FIFO_CTRL_REG || x || x || x || x || x || x || x || CLEAR || CLEAR = 1, clear the read FIFO. Bit is self-clearing.
 |-
-| $AF:AE20 || W || SDC_TX_FIFO_DATA_REG || colspan="8"|data || Write data block here.
+| $AF:EA20 || W || SDC_TX_FIFO_DATA_REG || colspan="8"|data || Write data block here.
 |-
-| $AF:AE21 || W || SDC_TX_FIFO_CTRL_REG || x || x || x || x || x || x || x || CLEAR || CLEAR = 1, clear the write FIFO. Bit is self-clearing.
+| $AF:EA21 || W || SDC_TX_FIFO_CTRL_REG || x || x || x || x || x || x || x || CLEAR || CLEAR = 1, clear the write FIFO. Bit is self-clearing.
 |}
-==== GABE: SDC_TRANS_ERROR_REG ($AF:AE05) ====
+==== GABE: SDC_TRANS_ERROR_REG ($AF:EA05) ====
 Lists any error conditions on reads, writes, or general transactions:

← Older revision		Revision as of 16:00, 14 March 2020
Line 704:		Line 704:

	=== GABE SDC Interface ($AF:EA00) ===		=== GABE SDC Interface ($AF:EA00) ===
		+
		+	GABE provides block-level access to the SPI interface of the SD card. Currently, there are other registers in that provide access to the SD card through a CH376S chip, but that interface should be considered deprecated in favor of this interface. Most FMX boards do not have the CH376S chip, leaving its position unpopulated on the board.
		+
		+	{\| class="wikitable"
		+	! Address !! R/W !! Name !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0 !! Description
		+	\|-
		+	\| $AF:AE00 \|\| R \|\| SDC_VERSION_REG \|\| colspan="8"\|version \|\| Should read 12
		+	\|-
		+	\| $AF:AE01 \|\| W \|\| SDC_CONTROL_REG \|\| x \|\| x \|\| x \|\| x \|\| x \|\| x \|\| x \|\| RESET \|\| Control register: RESET = 1 resets the core logic. Self clearing.
		+	\|-
		+	\| $AF:AE02 \|\| W \|\| SDC_TRANS_TYPE_REG \|\|x \|\| x \|\| x \|\| x \|\| x \|\| x \|\| colspan="2"\|TRANS \|\| Sets the type of transaction: 0 = Direct, 1 = INIT SD, 2 = Read Block, 3 = Write block
		+	\|-
		+	\| $AF:AE03 \|\| W \|\| SDC_TRANS_CONTROL_REG \|\| x \|\| x \|\| x \|\| x \|\| x \|\| x \|\| x \|\| START \|\| Start transaction bit.
		+	\|-
		+	\| $AF:AE04 \|\| R \|\| SDC_TRANS_STATUS_REG \|\| x \|\| x \|\| x \|\| x \|\| x \|\| x \|\| x \|\| BUSY \|\| Status of the transaction. BUSY = 1 indicates a transaction is in progress.
		+	\|-
		+	\| $AF:AE05 \|\| R \|\| SDC_TRANS_ERROR_REG \|\| x \|\| x \|\| colspan="2"\|WR_ERR \|\| colspan="2"\|RD_ERR \|\| colspan="2"\|TRANS_ERR \|\| Error conditions for read, write, and transaction.
		+	\|-
		+	\| $AF:AE06 \|\| RW \|\| SDC_DIRECT_ACCESS_REG \|\| colspan="8"\|data \|\| SPI Direct Read and Write - Set DATA before initiating direct Access Transaction
		+	\|-
		+	\| $AF:AE07 \|\| W \|\| SDC_SD_ADDR_7_0_REG \|\| A7 \|\| A6 \|\| A5 \|\| A4 \|\| A3 \|\| A2 \|\| A1 \|\| A0 \|\| Set the ADDR before a block read or block write.
		+	\|-
		+	\| $AF:AE08 \|\| W \|\| SDC_SD_ADDR_15_8_REG \|\| A15 \|\| A14 \|\| A13 \|\| A12 \|\| A11 \|\| A10 \|\| A9 \|\| A8 \|\| ADDR[8:0] always should be 0, since each block is 512 bytes
		+	\|-
		+	\| $AF:AE09 \|\| W \|\| SDC_SD_ADDR_23_16_REG \|\| A23 \|\| A22 \|\| A21 \|\| A20 \|\| A19 \|\| A18 \|\| A7 \|\| A6
		+	\|-
		+	\| $AF:AE0A \|\| W \|\| SDC_SD_ADDR_31_24_REG \|\| A32 \|\| A31 \|\| A30 \|\| A29 \|\| A28 \|\| A26 \|\| A25 \|\| A24
		+	\|-
		+	\| $AF:AE0B \|\| W \|\| SDC_SPI_CLK_DEL_REG \|\| colspan="8"\|clock delay
		+	\|-
		+	\| $AF:AE10 \|\| R \|\| SDC_RX_FIFO_DATA_REG \|\| colspan="8"\|data \|\| Data from block read
		+	\|-
		+	\| $AF:AE12 \|\| R \|\| SDC_RX_FIFO_DATA_CNT_HI \|\| CNT15 \|\| CNT14 \|\| CNT13 \|\| CNT12 \|\| CNT11 \|\| CNT10 \|\| CNT9 \|\| CNT8 \|\| How many bytes in the read FIFO (HI)
		+	\|-
		+	\| $AF:AE13 \|\| R \|\| SDC_RX_FIFO_DATA_CNT_LO \|\| CNT7 \|\| CNT6 \|\| CNT5 \|\| CNT4 \|\| CNT3 \|\| CNT2 \|\| CNT1 \|\| CNT0 \|\| How many bytes in the read FIFO (LOW)
		+	\|-
		+	\| $AF:AE14 \|\| W \|\| SDC_RX_FIFO_CTRL_REG \|\| x \|\| x \|\| x \|\| x \|\| x \|\| x \|\| x \|\| CLEAR \|\| CLEAR = 1, clear the read FIFO. Bit is self-clearing.
		+	\|-
		+	\| $AF:AE20 \|\| W \|\| SDC_TX_FIFO_DATA_REG \|\| colspan="8"\|data \|\| Write data block here.
		+	\|-
		+	\| $AF:AE21 \|\| W \|\| SDC_TX_FIFO_CTRL_REG \|\| x \|\| x \|\| x \|\| x \|\| x \|\| x \|\| x \|\| CLEAR \|\| CLEAR = 1, clear the write FIFO. Bit is self-clearing.
		+	\|}
		+
		+	==== GABE: SDC_TRANS_ERROR_REG ($AF:AE05) ====
		+
		+	Lists any error conditions on reads, writes, or general transactions:
		+
		+	{\| class="wikitable"
		+	\|+ TRANS_ERR codes [1:0]
		+	! Code !! Condition
		+	\|-
		+	\| 00 \|\| No INIT error
		+	\|-
		+	\| 01 \|\| INIT CMD0 error
		+	\|-
		+	\| 10 \|\| INIT CMD1 error
		+	\|}
		+
		+	{\| class="wikitable"
		+	\|+ RD_ERR codes [3:2]
		+	! Code !! Condition
		+	\|-
		+	\| 00 \|\| No read error
		+	\|-
		+	\| 01 \|\| CMD error
		+	\|-
		+	\| 10 \|\| Token error
		+	\|}
		+
		+	{\| class="wikitable"
		+	\|+ WR_ERR codes [5:4]
		+	! Code !! Condition
		+	\|-
		+	\| 00 \|\| No write error
		+	\|-
		+	\| 01 \|\| CMD error
		+	\|-
		+	\| 10 \|\| Data error
		+	\|-
		+	\| 11 \|\| Busy error
		+	\|}

	=== GABE SN76489 Interface ($AF:F100) ===		=== GABE SN76489 Interface ($AF:F100) ===

@@ Line 702: / Line 702: @@
 | 1 || 1 || Reserved
 |}
 === GABE SN76489 Interface ($AF:F100) ===

@@ Line 451: / Line 451: @@
 ! Address !! Name !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0 !! Description
 |-
-| $AF:E800 || JOYSTICK0 || BUTTON2 || BUTTON1 || 0 || BUTTON0 || RIGHT || LEFT || DOWN || UP || Right-most joystick port
+| $AF:E800 || JOYSTICK0 || BUTTON2 || BUTTON1 || 0 || BUTTON0 || RIGHT || LEFT || DOWN || UP || Left-most joystick port
 |-
 | $AF:E801 || JOYSTICK1 || BUTTON2 || BUTTON1 || 0 || BUTTON0 || RIGHT || LEFT || DOWN || UP || Next to joystick port 0
@@ Line 457: / Line 457: @@
 | $AF:E802 || JOYSTICK2 || 0 || 0 || 0 || BUTTON0 || RIGHT || LEFT || DOWN || UP || Next to joystick port 1
 |-
-| $AF:E803 || JOYSTICK3 || 0 || 0 || 0 || BUTTON0 || RIGHT || LEFT || DOWN || UP || Left-most joystick port
+| $AF:E803 || JOYSTICK3 || 0 || 0 || 0 || BUTTON0 || RIGHT || LEFT || DOWN || UP || Right-most joystick port
 |-
 | $AF:E804 || JOYSTICK_MODE || NES_TRIG || 0 || 0 || 0 || NES_DONE || NES_JOY || NES_EN1 || NES_EN0 || Control SNES compatibility

@@ Line 444: / Line 444: @@
 The joystick ports can be used in two modes: default mode, where they work like Atari style joysticks, and NES mode
 where they can interface with either NES or SNES game pads.
 {| class="wikitable"