View source for Gen-X 68040

At present, the GenX is functionally equivalent to an A2560K without the keyboard.

[https://256-foenix.us-east-1.linodeobjects.com/A2560K_UM_Rev0.0.2.pdf Manual]

Latest FPGA release:

Notes:

* Both displays show logos, but only display B is responsive.

Startup

* On hard-reset, the FPGA copies the first 64k of flash to $0.
* Post-upload reset leaves that block alone, so you can upload code there.
* Remember that the 68040 has THREE stacks: user, supervisor, and interrupt.  Reset puts you on the interrupt stack.

Memory

* With the latest pre-release FPGA load, burst access to SRAM and flash works in all modes.  This enables use of the MMU and all of the caching modes.
* If you wish to enable the caches, be sure to mark the I/O space as "serialized".  This should technically be done even if you aren't using the dcache. 
* At present, the DRAM is not stable.
* To test your own OS code, upload it to $0000:0000. 

I/O
* The SD Card detect bit doesn't appear to work (always thinks a card is present).
* If you wish to enable the caches, be sure to mark the I/O space as "serialized".  This should technically be done even if you aren't using the dcache. 
* Text display memory is byte-access only.
* VRAM writes go through a fifo.  At present, there is no way to read the VRAM (which, IMHO, is fine), and if the fifo fills up, the graphics engine will pause drawing to work the fifo.

Math Co-Pro
* Unsigned divide seems broken; might have heard it's using the same inputs as the signed divide.
* When running out of iCache, you need a NOP between writing the signed divide registers and reading back the result.

vasm

* The 68040 MOVEC cache and MMU control registers are there, but typically without the last letter (R for Register).
* Auto-alignment rules are brain-damaged: the assembler will re-align instructions but not their associated labels, and won't even warn you if constants are mis-aligned.  
** Ha!  The -align option forces natural alignment of data.  This fixes most of the problems. Just be sure to manually re-align after any byte data.

Ethernet

Whoa!!!  Finally managed to make lan interrupts work!!!  You need to do three things:
* Enable push/pull drive (apparently, there's no pull-up).
* Invert the polarity of the signal (GAVIN's polarity control doesn't appear to do anything).  The lan manual says that this setting is ignored in push/pull mode, but this is apparently not the case...
* Clear the condition in the lan before resetting the lan's IRQ.  In my case, this means draining the rx queue.  This is ... awkward, and could lead to race conditions, but we'll see.  Weirdly, clearing it before appears to change the chip's internal report, but not its external report...